1. Field of the Invention
The present invention relates to a stacked multi-chip package in which a plurality of chips are encapsulated in a stacked state, and to a process for fabricating a chip structuring the multi-chip package and to a wire-bonding process.
2. Description of the Related Art
In recent years, while increases in capability, function as well as the miniaturization of of electronic devices have been remarkable, further progress in raising the capabilities of mounted semiconductor devices and high-density packaging have been called for. Accordingly, the demand for stacked multi-chip packages, in which semiconductor devices are implemented three-dimensionally, for thin-form, high volume devices such as I.C. memory cards has become very considerable.
FIG. 12 shows a conventional stacked multi-chip package 100 in which semiconductor devices are mounted in three dimensions. The stacked multi-chip package 100 is structured by chips 102 and 104, a glass epoxy substrate 106, and solder balls 105. Chips 102 and 104 are formed at substantially the same size. Chips 102 and 104 are mounted on the glass epoxy substrate 106, and the solder balls 105 are provided at a lower face side of the glass epoxy substrate 106. Thus, the stacked multi-chip package 100 is a two-chip layer structure in which the chips 102 and 104 are stacked.
Hereinafter, the chip 102 is referred to as the upper chip 102 and the chip 104 is referred to as the lower chip 104. The upper chip 102 and the lower chip 104 are electrically connected, via gold wires (Au wires) 110, by a wire-bonding process with bonding posts 108 which are provided on the glass epoxy substrate 106.
Here, because the upper chip 102 and the lower chip 104 are formed so that they are substantially the same size, a spacer 112 is disposed between the upper chip 102 and the lower chip 104, and a gap is formed between the upper chip 102 and the lower chip 104 by the spacer 112. Thus, at least one connection between the lower chip 104 and the bonding posts 108 by one or more Au wires 110 is enabled.
However, in the stacked multi-chip package 100 having the structure described above, only the Au wires 110 are connected between the upper chip 102 and the lower chip 104, and the gap between the upper chip 102 and the lower chip 104 is not utilized effectively. Moreover, even though there are only two chips, the stacked multi-chip package 100 has substantially the same height as a three chip layer structure, and the resulting thickness of the stacked multi-chip package 100 is large. Consequently, the stacked multi-chip package 100 cannot be mounted in electronic devices of a standard size, generally where the maximum thickness is 1.4 mm, or a thin-form size, generally where the maximum thickness is 1.2 mm.
In consideration of the circumstances described above, an object of the present invention is to provide a thin-form stacked multi-chip package which can effectively utilize the space between the lower chip 104 and the upper chip 102 (or the glass epoxy substrate 106).
A stacked multi-chip package relating to a first aspect of the present invention is a stacked multi-chip package that includes: a substrate; a first chip fixed at the substrate, the first chip including a collar portion which faces an upper face of the substrate in a state such that a gap is provided between the upper face of the substrate and the collar portion; and a second chip disposed in a region downward of the collar portion and fixed at the substrate with out contacting the first chip.
In the structure described above, the first chip is fixed at the upper face of the substrate. The collar portion, which opposes the upper face of the substrate, is provided at the first chip in a state such that the gap is provided between the first chip and the upper face of the substrate. The second chip is disposed in a region downward of the collar portion, and is fixed to the substrate so as not to make contact with the first chip.
Accordingly, the gap can be provided between the first chip and the substrate because the collar portion is formed at the first chip. Consequently, disposing the second chip in this gap is possible.
Because the second chip is fixed to the substrate in a state of not contacting with the first chip, a gap is formed between the second chip and the collar portion. Thus, the second chip can be directly connected with the substrate by metallic wires such as gold wires (Au wires) or the like. Consequently, the first chip and the substrate can be connected with metallic wires or the like without a spacer being disposed between the first chip and the substrate.
Accordingly, the cost of material for a spacer can be saved and, because a spacer is not used, the number of components is decreased, there are fewer production steps, and productivity is improved. Moreover, because the first chip is directly fixed to the substrate, stability of the first chip is better than in a case in which a first chip is fixed to a substrate via a spacer, and reflow resistance is improved. Furthermore, because the collar portion is provided at the first chip, surface area can be made greater.
In the first aspect, the first chip may be substantially T-shaped in cross-section.
The gap formed between the upper face of the substrate and the collar portion may be set to a size such that the collar portion does not make contact with connection members which electrically connect the second chip with the substrate. Accordingly, the second chip and the substrate can be directly connected by metallic wires.
An insulating member may be provided at a rear face side of the collar portion. Thus, there will be no problems even if the metallic wires, which electrically connect the second chip with the substrate, make contact with the insulating member. Therefore, a rising height of the connection members when the connection members are connected by a bonding device is not restricted.
Consequently, a level of precision of the bonding device that would be required for lowering the rising height of the connection members can be reduced, and a degree of freedom of the bonding device to be used can be increased.
Electrode pads, which are electrically connected with the connection members, are provided at the second chip. These electrode pads may be formed of nickel and gold. Accordingly, due to the electrode pads being formed of nickel and gold, the electrode pads play a role as impact absorbers, and bonding from the bonding posts on the substrate to the electrode pads on the second chip is enabled.
The connection members may be metallic wires, and these metallic wires are wired from the substrate to the second chip. Thus, because the metallic wires are wired from the substrate to the second chip, the metallic wires rise at the bonding posts side provided at the substrate, and peak portions of the metallic wires at the second chip side can be made lower. Accordingly, the gap formed between the first chip and the second chip can be made smaller, and thickness of the stacked multi-chip package can be made thinner.
Yet further again, the first chip may be specified to be a logic device and the second chip may be specified to be a storage device. Ordinarily, the profile of a logic device is larger than that of a storage device. Therefore, by making the first chip a logic device and making the second chip a storage device, it is intended that the stacked multi-chip package can be made more compact.
Furthermore, in the first aspect, a third chip may be interposed between the first and second chips and the substrate. The profile of the third chip is substantially the same as the profile of the first chip. Accordingly, in a state in which the second chip is fixed to the third chip, end faces of the second chip are disposed at an inner side from end faces of the third chip. Consequently, the third chip can also be connected with the substrate by metallic wires. Hence, a three-chip layer structure can be provided. Moreover, because the profile of the third chip is substantially the same size as the profile of the first chip, a population area is larger with the same area of chips.
The first chip and the substrate may be electrically connected by metallic wires wired from the first chip to the substrate, and the thickness of the collar portion set to substantially half of the thickness of the first chip.
A stacked multi-chip package relating to a second aspect of the present invention is a stacked multi-chip package that includes: a substrate; a first chip including an upper face which includes a first electrode pad, a lower face whose area is smaller than an area of the upper face, and a side face connecting the upper face and the lower face, the lower face being fixed on the substrate; first metallic wire electrically connecting the first electrode pad with the substrate; a second chip disposed below the first chip and including an upper face which includes a second electrode pad, the second chip being disposed at a location separated by a predetermined distance from the side face of the first chip; and second metallic wire electrically connecting the second electrode pad with the substrate.
In the second aspect, the first chip may be substantially T-shaped in cross-section.
A distance from the upper face of the second chip to the side face may be larger than a distance from the upper face of the second chip to a peak portion of the second metallic wires. Consequently, the second chip and the substrate can be directly connected by the metallic wires.
An insulating member may be provided at the side face. Thus, there will be no problems even when the metallic wires, which electrically connect the second chip with the substrate, make contact with the insulating member. Therefore, a rising height of the second metallic wires when the second metallic wires are connected by a bonding device is not restricted.
Consequently, a level of precision of the bonding device that would be required for lowering the rising height of the second metallic wires can be reduced, and a degree of freedom of the bonding device to be used can be increased.
The second electrode pads may be formed of nickel and gold. Accordingly, due to the second electrode pads being formed of nickel and gold, the second electrode pads play a role as impact absorbers, and bonding from the bonding posts at the substrate side to the second electrode pads is enabled.
The second metallic wires may be wired from the substrate to the second chip. Thus, because the second metallic wires are wired from the substrate to the second chip, the second metallic wires rise at the bonding posts side provided at the substrate, and peak portions of the second metallic wires at the second chip side can be made lower. Accordingly, the distance between the side face of the first chip and the lower face of the second chip can be made smaller, and thickness of the stacked multi-chip package can be made thinner.
In the second aspect, the first chip may be specified to be a logic device and the second chip may be specified to be a storage device. Due to the profiles of logic devices being larger than those of storage devices, it is intended that the stacked multi-chip package can be made more compact by making the first chip a logic device and the second chip a storage device.
A third chip may be interposed between the first and second chips and the substrate. The profile of the third chip is substantially the same as the profile of the first chip.
Accordingly, in a state in which the second chip is fixed to the third chip, end faces of the second chip are disposed at an inner side from end faces of the third chip. Consequently, the third chip can also be connected with the substrate by metallic wires. Hence, a three-chip layer structure can be provided. Moreover, because the profile of the third chip is substantially the same as the profile of the first chip, a population area is larger with the same area of chips.
A process for fabricating a chip provided with a collar portion, relating to a third aspect of the present invention, is a process that includes: machining mutually parallel recess portions in one face of a wafer at which a plurality of chips are coplanarly disposed; machining recess portions which are transverse with respect to the mutually parallel recess portions; and cutting the wafer along width direction center lines of the respective recess portions.
A process for fabricating a chip provided with a collar portion, relating to a fourth aspect of the present invention, is a process that includes: etching mutually parallel recess portions in one face of a wafer at which a plurality of chips are coplanarly disposed; etching recess portions which are transverse with respect to the mutually parallel recess portions; and cutting the wafer along width direction center lines of the respective recess portions.
A process for wire-bonding a chip relating to a fifth aspect of the present invention is a process that includes: forming an electrode pad with nickel and gold, to which metallic wire can be attached for electrically connecting the chip with a substrate; and wiring the metallic wire from the substrate to the chip.
Consequently, the metallic wires rise at the bonding posts side provided at the substrate, and peak portions of the metallic wires at the second chip side can be made lower. Accordingly, a distance between a side face of a first chip and a lower face of a second chip can be made smaller, and thickness of a stacked multi-chip package can be made thinner.
A stacked multi-chip package relating to a sixth aspect of the present invention is a stacked multi-chip package that includes: a substrate including a front face; a chip body fixed at the front face of the substrate and including a first face, with a gap being formed between the first face and the front face of the substrate, and a connecting portion which connects the chip body with the substrate; and a fixed chip fixed at the front face of the substrate with out contacting the chip body, at least a portion of the fixed chip being disposed in the gap, wherein the portion of the fixed chip includes an upper face which opposes the first face of the chip body, and the upper face is disposed upward relative to the connecting portion.
A stacked multi-chip package relating to a seventh aspect of the present invention is a stacked multi-chip package according to the sixth aspect, in which the chip body further includes: a chip disposed to be separated a predetermined distance upward from the front face of the substrate; and a spacer disposed between the chip and the substrate.